Systematic formal verification for fault-tolerant time-triggered algorithms

Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms

Many critical real-time applications are implemented as time-triggered systems. We present a systematic way to derive such time-triggered implementations from algorithms specified as functional programs (in which form their correctness and fault-tolerance properties can be formally and mechanically verified with relative ease). The functional program is first transformed into an untimed synchro...

Rushby : Formal Verification for Time - Triggered Algorithms

Formal analysis of fault tolerant algorithms in the time-triggered architecture

Formal Model Layers The basis for the formal analysis work has been given in Chapter 2. It introduces adequate formal models to analyse distributed algorithms at different levels of abstraction. We have presented a formalization of the untimed synchronous system model, and a ground model for time-triggered systems. In particular, we have introduced abstract models of the communication network t...

A fault tolerant dynamic time triggered protocol

The increasing use of embedded networks in safety-critical systems, for example in the automotive and avionics fields, comes with additional requirements like real-time capabilities and fault-tolerance. This work presents the new fault-tolerant real-time protocol TEA, which provides the ability of fault-tolerant dynamic arbitration, in opposite to already present protocols. TEA tolerates single...

Verification of Fault-Tolerant Clock Synchronization Algorithms

In this paper, we propose a benchmark for verification of properties of fault-tolerant clock synchronization algorithms, namely, a benchmark of a TTEthernet network, where properties of the clock synchronization algorithm as implemented in a TTEthernet network can be verified, and optimization techniques for verification purposes can be applied. Our benchmark, which assumes non-faulty component...